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AR# 61572

MIG 7 Series - DDR3 - Maximum PHY limits for TwinDie components


For 7 Series MIG DDR3 design, the Twin die (dual rank) component maximum speed supported is one memory speed grade lower than dual rank DIMM. 

The maximum DDR3 rates are as follows.
FPGA Speed Grade Maximum Supported DDR3 Rate
-3 1333 Mb/s
-2 1333 Mb/s
-1 1066 Mb/s


There is currently only one TwinDie part included in the MIG GUI list, MT41K512M8THD-15E.  

However MIG currently limits this device to 1066 Mb/s operation for all speed grades. 

In order to target a TwinDie component at 1333 Mb/s, top level RTL parameters will need to be modified.  

Below is a list of clocking related parameters that need to change when increasing from 1066 Mb/s to 1333 Mb/s (when the input sys_clk period is kept at 1875 ps):

   parameter CL                    = 9,                        //previously '7'

  parameter CWL                   = 7,                   //previously '6'

  parameter CLKFBOUT_MULT         = 5,    //previously '4'

  parameter tCK                   = 1500,                             //previously '1875'

Above 1066 Mb/s operation, the following IODELAY parameters must also be enabled:

   parameter IDELAY_ADJ            = "ON",  

   parameter FINE_PER_BIT          = "ON",  

   parameter CENTER_COMP_MODE      = "ON",  

   parameter PI_VAL_ADJ            = "ON",

   parameter REF_CLK_MMCM_IODELAY_CTRL    = "TRUE",


By default Vivado generates a .dcp synthesized checkpoint file for each IP when the output products are generated for that core.  

Since the underlying MIG RTL needs to be modified, there are a few steps that need to be followed in order to make these edits and properly regenerate the out-of-context synthesis run for MIG:


1.            Select the MIG .xci file in the GUI, go to properties and uncheck IS_MANAGED.

2.            Right click the .xci, go to IP Hierarchy -> Show IP Hierarchy.

3.            Double click on <core_name>_mig.v and <core_name>_sim.v under the .xci to edit the top level parameters.

4.            Modify the parameters above and save the files.

5.            Under the Design Runs tab at the bottom, right click on <core_name>_synth_1 and click "Reset Runs"

6.            Now when you implement the design, the out-of-context synthesis run for MIG will be re-run and an updated .dcp file will be generated.


If a scripted flow is used instead of the GUI, the Verilog files can be modified in a text editor and then the MIG out-of-context synthesis run can be re-run with a command similar to this:

reset_run mig_7series_0_synth_1
launch_runs mig_7series_0_synth_1


Revision History:

 07/30/2014 - Initial Release

AR# 61572
Date 10/22/2014
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2014.2
  • MIG 7 Series
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