Up to Vivado 2014.3, MIG UltraScale generates "ddr4_par" as an output I/O for all DDR4 designs.
The DDR4 PAR feature is only used by MIG for RDIMM designs.
Therefore, this pin is not used or needed when interfacing with a component, SODIMM, or UDIMM.
Starting with the MIG release associated with Vivado 2014.3, the "ddr4_par" output will be removed to reduce the Addr/Cont pin count by one.
For designs that have PAR connected from the FPGA to a component, SODIMM, or UDIMM, the PAR output of the FPGA should be driven low using an SSTL12 driver to ensure it is held low at the memory.
For designs that do not connect PAR, refer to the Pin and Bank Rules within PG150.