This downloadable PDF of an Answer Record is provided to enhance its usability and readability.
It is important to note that Answer Records are Web-based content that are frequently updated as new information becomes available.
You are reminded to visit the Xilinx Technical Support Website and review (Xilinx Answer 61596) for the latest version of this Answer.
This answer record contains screen captures of tables and figures from other documents.
The guidelines provided might have changed in the latest release of those documents.
The readers are advised to refer to the latest release of the corresponding documents.
PCIe Link training and stability issues make up the vast majority of the issues in interlink connectivity.
This document describes the use case for debugging these issues with the integrated tools in the Xilinx Vivado Design Suite.
This document will be focused on the use of Vivado ILA for debug by capturing link training debug signals in the 7 Series Integrated Block for PCIe IP core, and is also applicable to the AXI Memory Mapped PCIe Bridge core when it is used on a 7 Series part.
The document does not go into detail on
the background of link training issues.
For detailed information on debugging link training issues in the 7 Series Integrated Block for PCI Express core, refer to (Xilinx Answer 56616).
07/25/2015 - Initial Release
|Name||File Size||File Type|
|Vivado ILA Usage Guide for 7 Series Integrated Block for PCI Express||2 MB|