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AR# 61626

LogiCORE IP UltraScale Architecture Integrated Block for 100G Ethernet - How do I speed up simulation time?

Description

With the 2014.4/2015.1 example design, simulation takes 2 hours to complete in ModelSim and 30 minutes to complete in IES.

Vivado simulator can take up to 6 hours to complete.

Is there a way to speed up the simulation?

Solution

Simulations involving the complex transceiver models can take long periods of time.

If your simulation involves the 100GE Ethernet IP operating in a loopback scenario, an additional method to improve simulation time is to reduce the PCS lane Alignment Marker (AM) spacing in order to speed up the time the IP will take to achieve PCS Lane lock.

A `define SIM_SPEED_UP can be set when using Vivado 2014.4.1 or later to change CTL_TX_VL_LENGTH_MINUS1 and CTL_RX_VL_LENGTH_MINUS1 from 16'h3FFF to 16'h03FF.

Note:

1) Altering the value of CTL_TX_VL_LENGTH_MINUS1 and CTL_RX_VL_LENGTH_MINUS1 from the default value of 0x3FFF will violate the IEEE 802.3 spec.

2) Decreasing the AM spacing will result in less than 100GE bandwidth being available on the link.

3) This change can be made only in simulation. For a design to work in hardware, the default value of 0x3FFF must be used.

4) Full rate simulation without the SIM_SPEED_UP option should still be run.

 

 

VCS

Use the vlogan option: +define+SIM_SPEED_UP

ModelSim

Use the vlog option: +define+SIM_SPEED_UP

IES

Use the ncvlog option: +define+SIM_SPEED_UP

Vivado Simulator

Use the xvlog option: -d SIM_SPEED_UP

 

Revision History

07/25/2014 Initial Release
03/30/2015 Update to include 'define SIM_SPEED_UP
AR# 61626
Date Created 07/25/2014
Last Updated 09/01/2016
Status Active
Type General Article
IP
  • UltraScale - CMAC