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AR# 61637

Zynq-7000 AP SoC, SMC Parallel (SRAM/NOR) Interface Does Not Correctly Assert CS0 For 64 MB Memories


Chip Select 0 (CS0) does not go active when accessing an address in the range 0xE4000000 - 0xE5FFFFFF in the SRAM/NOR interface when the memory controller is configured to access a 64 MB memory device.



Impact:                   Minor. 

Work-around:        You can implement either of the following workarounds:


Workaround 1:

Description: A board circuitry can be implemented as a workaround for ADDR 25 inversion and Chip Select assertion.

Below are the steps:

  1. Implement a two input AND gate - the two inputs come from  the MIO0 and MIO1 outputs from the Zynq-7000 SoC.
    Connect the AND gate output to the NOR flash devices chip enable input.

  2. Connect the MIO0 output from the Zynq-7000 SoC to the ADDR 25 input of the NOR device.

  3. Configure MIO0 as Chip Select 0 and MIO1 as Chip Select 1.


Workaround 2:

Description:  A GPIO based control can be implemented for Chip Select assertion.

Configure MIO0 as GPIO and drive constant 0.

This can be done as part of the NOR flash initialization. 

Connect it to the chip enable input of the NOR flash device.


Configurations Affected :

All Zynq devices with SRAM/NOR interface enabled for 64MB memory access. 

There is currently no plan to fix this issue.

Please refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record.



Use the PS7 Configuration Wizard from Vivado Design Suite 2014.3 OR If writing your own FSBL use work-around 2  OR update the board layout with workaround 1.

AR# 61637
Date Created 07/28/2014
Last Updated 08/22/2014
Status Active
Type Design Advisory
  • Zynq-7000