Chip Select 0 (CS0) does not go active when accessing an address in the range 0xE4000000 - 0xE5FFFFFF in the SRAM/NOR interface when the memory controller is configured to access a 64 MB memory device.
Work-around: You can implement either of the following workarounds:
Description: A board circuitry can be implemented as a workaround for ADDR 25 inversion and Chip Select assertion.
Below are the steps:
Description: A GPIO based control can be implemented for Chip Select assertion.
Configure MIO0 as GPIO and drive constant 0.
This can be done as part of the NOR flash initialization.
Connect it to the chip enable input of the NOR flash device.
Configurations Affected :
All Zynq devices with SRAM/NOR interface enabled for 64MB memory access.
There is currently no plan to fix this issue.
Please refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record.
Use the PS7 Configuration Wizard from Vivado Design Suite 2014.3 OR If writing your own FSBL use work-around 2 OR update the board layout with workaround 1.