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AR# 61736

SEM IP Soft Error Mitigation - What is the valid range of addresses for error injection by LFA targeting Spartan 6 devices?


The SEM IP error injection capability is a useful feature that enables hardware-based evaluation of the SEM IP functionality, enables testing to confirm that the IP has been integrated into the larger design as intended, and enables testing of the larger design as intended.

When performing error injection into the configuration memory, Xilinx recommends following the guidance in (Xilinx Answer 61241) Soft Error Mitigation IP Guidance for testing with error injection.


For Spartan-6 devices, the range of valid LFA for error injection and detection is from LFA 0000000 to LFA Maximum Frame (MF).

The maximum Frame value for the target device is available by using the "Status Report" command with the monitor interface.

The values are also available in the tables below.

According to which GT are used in the design, start address or max address range is set differently at time of SEM IP generation.

Error injection should also be limited to the same range as IP is configured to scan for errors.

See (Xilinx Answer 52716) Design Advisory for Spartan-6 FPGAs - Configuration Readback including SEM_IP or POST_CRC causes power distribution network noise affecting SelectIO and GTP interfaces

NO GTs in these devices. All type 0 frames covered Bottom Address Upper Address
SF (decimal) SF (hex) MF (decimal) MF (hex)
LX4 0 0 2026 7EA
LX9 0 0 2026 7EA
LX16 0 0 2974 B9E
LX25 0 0 5063 13C7
LX45 0 0 9086 237E
LX75 0 0 15382 3C16
LX100 0 0 20302 4F4E
LX150 0 0 27238 6A66
LXT devices - but NO GT rows are skipped (same range as above). All type 0 frames covered Bottom Address Upper Address
SF (decimal) SF (hex) MF (decimal) MF (hex)
LX25T 0 0 5063 13C7
LX45T 0 0 9086 237E
LX75T 0 0 15382 3C16
LX100T 0 0 20302 4F4E
LX150T 0 0 27238 6A66
LXT devices. Skipping top GT row reduces MF Bottom Address Upper Address
MF (decimal) MF (hex)
LX25T 4050 FD2
LX45T 7950 1F0E
LX75T 14100 3714
LX100T 18610 48B2
LX150T 24968 6188
LXT devices. Skipping bottom GT row increases SF Bottom Address Upper Address
SF (decimal) SF (hex)
LX75T 1280 500
LX100T 1690 69A
LX150T 2268 8DC
AR# 61736
Date Created 08/10/2014
Last Updated 10/22/2015
Status Active
Type General Article
  • Spartan-6
  • Soft Error Mitigation