UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61744

MIG 7 Series DDR3 - ECC Multiple errors are seen in hardware when targeting Vivado 2014.2. Errors were not seen in previous versions.

Description

Version Found: MIG v2.1
Version Resolved: See (Xilinx Answer 54025)

When running a DDR3 interface with ECC enabled in hardware, multiple ECC errors are issued. 

These are errors that were not seen in previous versions.

Solution

This is a known issue with the ECC generation rtl . 

A change in the Vivado 2014.2 tools resulted in a different rtl optimization that uncovered the rtl issue.  

To work around the issue, replace the mig_7series_v2_1_ecc_gen.v module generated by MIG with the module attached to this answer record.  

This rtl file is located in the "core_name\user_design\rtl\ecc" directory.

Note: When rtl updates are made, out-of-context (OOC) synthesis must be disabled.

Revision History:
08/29/2014 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
mig_7series_v2_1_ecc_gen.v 7 KB V
AR# 61744
Date Created 08/11/2014
Last Updated 09/16/2014
Status Active
Type Known Issues
Devices
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite - 2014.2
IP
  • MIG 7 Series