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AR# 61841

Vivado Sysgen - How can I add a Xilinx IP Catalog IP into the Black Box block in the Xilinx Blockset and be able to both simulate and generate the Hardware Cosimulation target?

Description

How can I add a Xilinx IP Catalog IP into the Black Box block in the Xilinx Blockset?

I also wish to be able to both simulate and generate the Hardware Cosimulation target.

Solution

It is necessary to add files for both Simulation and Synthesis.

For simulation, the simulation model is required, and for Synthesis, you need to add the DCP file for the generated IP in the "_config.m" file.

When adding the associated files for the black box, use the following syntax:

  if (strcmp(this_block.getConfigPhaseString(),'config_simulation'))

     this_block.addFile('addsub_funcsim.vhd','addsub_funcsim.vhd');

  else

     this_block.addFile('addsub.dcp');

  end;

 this_block.addFile('addsub_stub.vhd');

Note: For IP cores from the catalog that deliver encrypted simulation models, you will need to add that file to the black box but also give that file its own individual file.

 

For non-encrypted simulation models, this is not necessary as the contents of the file can be added to the overall simulation model generated for the complete design.

 

As a result the above code would change to look like the following:

if (strcmp(this_block.getConfigPhaseString(),'config_simulation'))

     this_block.addFile('addsub_funcsim.vhd');

  else

     this_block.addFile('addsub.dcp');

  end;

 this_block.addFile('addsub_stub.vhd');

Note: Make sure that the file extension for the included HDL code is either .v or .vhd, do not use .vhdl.

AR# 61841
Date Created 08/26/2014
Last Updated 08/10/2015
Status Active
Type General Article
Tools
  • System Generator for DSP
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2014.2
  • More
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
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