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AR# 61846

2014.2 - Vivado Simulator - Simulating the Zynq System Example Project in VCS


I'm trying to simulate the Zynq System Example design in VCS and getting errors. How do I get past these?


Make sure you have done the following:

1) Use VCS Version I-2014.03. Compile the libraries to a specific directory and then change the LIBRARY_SCAN option to TRUE

2) In the Vivado project, delete the VHDL wrapper file and change the target language (Project Settings -> General) to Verilog. Now right-click on the *.bd file in the sources heirarchy and generate an HDL wrapper. This should now be in Verilog. Now right-click the bd file again and select 'Generate Output Products'

3) Run export_simulation and point to the location in (1). In the generated shell file from export simulation (tb_sim_vcs_mx.sh), change the vcs_opts to include:

-load $XILINX_VIVADO/lib/lnx64.o/libxil_vcs.so:xilinx_register_systf 

For example this is what it would look like with this option added:

vcs_opts="-load $XILINX_VIVADO/lib/lnx64.o/libxil_vcs.so:xilinx_register_systf -full64 -debug_pp -t ps -licwait -60 -l tb_comp.log"

4) Set the following enviorment variable in your Linux shell:


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58891 Xilinx Simulation Solution Center - Design Assistant - Third Party Simulators - Synopsys VCS​/VCS-MX N/A N/A
AR# 61846
Date Created 08/26/2014
Last Updated 04/02/2015
Status Active
Type General Article
  • FPGA Device Families
  • Vivado Design Suite