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AR# 61861

Zynq-7000 AP SoC, I2C - Missing Glitch Filter Implementation in Zynq PS I2C Controller

Description

The I2C controller specification v2.1 specifies the filtering out of glitches spanning a maximum of 50 ns on the SDA and SCL lines in the fast mode of operation.

The I2C controller in Zynq-7000 AP SoCs PS7 does not implement the circuitry to filter these glitches. 

A glitch on the SDA or SCL line can cause a momentary false trigger on the signal line. 

A glitch on SDA could result in an incorrect START condition or an incorrect STOP condition being recognized, thus breaking the bus protocol. 

A glitch on SCL could result in incorrect data transfer, also breaking bus protocol. 

In both cases, data transfer is corrupted and the bus could hang.

In order to avoid this situation, the user needs to implement a circuitry to filter out glitches from SDA and SCL lines.
 

Solution

Impact

Major.

The user needs to implement circuitry to filter out the glitch on SCL and SDA externally before interfacing the signals with the controller.

 

Work-around:

The user can implement the following workaround in the Programmable Logic portion of Zynq or in an external programmable device like CPLD.

The glitch filter circuitry is composed of metastability flops and debouncer logic on SDA and SCL signals.

The logic works on a faster clock domain which is capable of sampling the glitch occurring on SDA and SCL signals.

SDA and SCL signals are passed through a three stage synchronizer to eliminate metastability.

The logic requires a faster clock to filter out the glitch and the frequency of the clock should be at least 40 MHz.

However using a faster frequency clock source eliminates the possibility of extending the glitch to be filtered significantly due to the presence of the metastability flops.

The recommended clock frequency is 100 MHz.

The procedure for glitch filtering is:

  1. Detect a transition on an SDA or SCL signal.

    The user needs to implement independent glitch filtering circuitry for SDA and SCL.


  2. When the edge is detected, load a counter with the number of clock cycles for which debouncing is required (this should result in 50 ns debouncing of SDA and SCL signal).
    Continue decrementing the counter.
     
  3. Until the counter is decremented to 0, assert the previous state of bus in the output lines.
    If the signal value changes again, reset the counter without changing the signal value.
    This eliminates any glitch.
     
  4. Once the counter is decremented to 0, if the signal has not changed, then assign the new value of SCL and SDA on the output signal.


Note: Both SCL and SDA signals need to be debounced by 50 ns so that the timing relationship between SCL and SDA remains unchanged.

The user can refer to the attached code snippet which serves as an example. 

Configurations Affected:

All Zynq devices using the I2C controller as a master.

Device Revision(s) Affected:

All, no plan to fix.

Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences

Resolution:                

This is a third-party errata; this will not be fixed.

Attachments

Associated Attachments

Name File Size File Type
filter.vhd 7 KB VHD
debounce.vhd 7 KB VHD
AR# 61861
Date Created 08/27/2014
Last Updated 04/01/2016
Status Active
Type Design Advisory
Devices
  • XA Zynq-7000
  • Zynq-7000
  • Zynq-7000Q