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AR# 61875

Design Advisory for QPLL based 7 Series FPGA GTX/GTH designs: QPLLPD should not be enabled for min time of 500ns after configuration is complete


For QPLL based 7 series GTX/GTH designs, QPLLPD should not be set HIGH for a minimum time of 500ns after configuration is complete.

This new requirement is the same as the already documented requirement for GT[TX/RX]RESET.
The Vivado 2014.2 7 Series Transceivers Wizard generates a QPLLPD logic in the example design when QPLL is selected as clock source.
This logic should not be used. 


QPLL powerdown (QPLLPDis not required to reset or initialize the transceivers.

If QPLLPD is required to save power, QPLL powerdown can be done after transceiver initialization successfully completes.

(The minimum wait time from configuration complete is 500ns).
QPLLPD logic will be deleted from Vivado 2014.3 and the new requirement will be documented in transceivers user guide UG476.
QPLLPD can be tied to 1'b1 by default only if QPLL is not used or selected as the PLL clock source for transceivers.
CPLLPD does not have this requirement. 
AR# 61875
Date Created 08/28/2014
Last Updated 09/26/2014
Status Active
Type Design Advisory
  • Kintex-7
  • Kintex-7Q
  • Virtex-7
  • Virtex-7Q
  • Vivado Design Suite - 2014.2
  • 7 Series FPGAs Transceivers Wizard
Boards & Kits
  • Kintex-7 Boards and Kits
  • Virtex-7 Boards and Kits