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AR# 61898

AXI Bridge for PCI Express Gen3 - Release Notes and Known Issues for Vivado 2014.3 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the AXI Bridge for PCI Express Gen3 Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2014.3 and newer tool versions.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

 

Supported devices can be found in the following three locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
  • AXI Bridge for PCI Express Gen3 Product Guide (PG194)

Changes in v3.0

 

  • Port Change:
    • Added pipe_{rx/tx}_{8-15}_sigs ports to support pipe simulation in UltraScale+ x16 configuration
    • Removed axi_ctl_aclk port for new IP creation. IP that have been upgraded is not affected
  • Other:
    • Added support for FLG1155/FLG1931 packages for xc7vh580t device, FLG1931 for xc7vh870t device, FFV1156/FFV1761 for xc7vx330t device, FFV1157/FFV1158/FFV1927 for xc7vx415T device
    • AXIBAR_NUM, BASEADDR, and HIGHADDR parameters are now converted to upper-case to improve driver backward compatibility with AXI Memory Mapped to PCI Express for 7 Series IP
    • Revision change in one or more subcores

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
v3.0 2016.3
v2.1 (Rev1)
2016.2
v2.1 2016.1
v2.0 (Rev1) 2015.4
v2.0 2015.3
v1.1 (Rev1) 2015.2.1
v1.1 (Rev1) 2015.2
v1.1 2015.1
v1.0 (Rev2) 2014.4
v1.0 (Rev1) 2014.4
v1.0 2014.3

 

Tactical Patch

The following table provides a list of tactical patches for the AXI Bridge for PCI Express Gen3 applicable to corresponding Vivado tool versions.

Answer Record Core Version (After installing the Patch) Tool Version Issues Fixed
(Xilinx Answer 63113)
v1.0 (Rev. 2) 2014.4 (Xilinx Answer 63113)
(Xilinx Answer 65744) v2.0 (Rev. 65744) 2015.3 (Xilinx Answer 65744)
(Xilinx Answer 65831) v2.0 (Rev. 65831) 2015.3 (Xilinx Answer 65744),(Xilinx Answer 65831)
(Xilinx Answer 67440) v2.1 (Rev. 67440) 2016.1 (Xilinx Answer 67440)

 

Known and Resolved Issues

The following table provides known issues for the AXI Bridge for PCI Express Gen3 core, starting with v1.0, initially released in Vivado 2014.3.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version Found Version Resolved
(Xilinx Answer 67422) Link up failure after multiple resets v2.1(Rev1) v3.0
(Xilinx Answer 67440) [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'axi_pcie3_0' v2.1 v2.1 (Rev1)
(Xilinx Answer 65569) Virtex-7 GTH QPLL temperature compensation attribute update   v2.1 (Rev1)
(Xilinx Answer 67172) Example Design Simulation with VCS Simulator hangs indefinitely v2.1 Not Resolved Yet
(Xilinx Answer 65831) GT DRP Ports disabled when Falling Edge Receiver Detect is selected v2.0 Not Resolved Yet
(Xilinx Answer 65744) Enabling both MSI and MSI-X in the same design v2.0 Not Resolved Yet
(Xilinx Answer 65500) Example Design Simulation with VCS Simulator Fails v2.0 Not Resolved Yet
(Xilinx Answer 65462) Link Up Bit (Bit[11]) in Phy Status Register is Not Asserted v2.0 v2.0 (Rev1)
(Xilinx Answer 64829)
AXI Master/Slave Outstanding Read/Write Transactions Limitation v1.1(Rev1) v2.0
(Xilinx Answer 63113)
Memory Read may not work in specific conditions v1.0(Rev1) v1.0(Rev2)
(Xilinx Answer 62515) VC709 example design fails during implementation v1.0 v1.0(Rev1)
(Xilinx Answer 62065) Questa Simulation fails with SIGABRT error v1.0 Fixed in QuestaSim 10.3c_1

Other Information:

 

(Xilinx Answer 63077) s_axis_arready is not asserted by default
(Xilinx Answer 65074) TSK_TX_MEMORY_WRITE_32 uses the incorrect value of tkeep


Revision History:

10/02/2014 Initial release
11/24/2014 Updated for 2014.4 Release
12/17/2014 Added (Xilinx Answer 63077)
01/07/2015 Added (Xilinx Answer 63113)
04/15/2015 Updated for 2015.1 Release
06/24/2015 Updated for 2015.2 Release
10/06/2015 Updated for 2015.3 Release
11/24/2015 Updated for 2015.4 Release
04/13/2016 Updated for 2016.1 Release
05/12/2016 Added (Xilinx Answer 67172)
09/08/2016 Updated for 2016.2 Release
07/05/2016 Added (Xilinx Answer 65569)
08/19/2016 Added (Xilinx Answer 67422)
10/05/2016 Updated for 2016.3 Release
AR# 61898
Date Created 09/02/2014
Last Updated 10/13/2016
Status Active
Type Release Notes
IP
  • AXI PCIe Gen3