We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6192

Synopsys FPGA Compiler: writes out absolete timing constrains in XNF (basnu:179)


Keywords: FPGA, Compiler, NGDBUILD, basnu, 179, timespec, obsolete

Urgency: Standard

General Description:

FPGA Compiler writes out timing constrains which may look like:

SYM, TSR22, TIMESPEC, TS186=P2S:75.00:reset, TS187=P2S:142.00:scan,
TS188=P2S:75.00:reset, TS189=P2S:75.00:start, TS190=P2S:75.00:reset,

P2S:75:reset is in absolete form and NGDBUILD (Translate) gives warnings:

WARNING:basnu:179 - Timespec "TS0 = C2S:75.00" is an obsolete form and will not be translated.


Entering the following line in your .synopsys_dc_setup will fix this problem:

xnfout_constraints_per_endpoint = 0
AR# 6192
Date Created 04/14/1999
Last Updated 08/31/2001
Status Archive
Type General Article