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AR# 61922

Vivado Synthesis - Does Vivado Synthesis make use of the parity bits for Asymmetric block RAM (BRAM) inference?

Description

Does Vivado Synthesis make use of the parity bits for Asymmetric block RAM inference?

For example, when the write port is 9x4K and the read port is 36x1K, it fits into a single block RAM if the parity bits are used for the read port.

Otherwise, it consumes 2 block RAMs without using the parity bits.

Solution

Vivado Synthesis does not support parity bits for Asymmetric block RAM inference.

As a result you might see more block RAM utilization than expected when port width is 36 for asymmetric RAM.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
57854 2014.1 Vivado Synthesis - Some patterns of asymmetric BRAM inference are not successful. N/A N/A
AR# 61922
Date Created 09/04/2014
Last Updated 04/05/2016
Status Active
Type Known Issues
Tools
  • Vivado Design Suite