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AR# 61930

Design Advisory Master Answer Record for Virtex UltraScale FPGA

Description

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the Virtex UltraScale FPGA and related issues which impact Virtex UltraScale FPGA designs.

Solution

Design Advisory Alerted on June 19th, 2017

(Xilinx Answer 69152)Design Advisory 2017.1 Tactical Patch for Vivado bi-directional logic issue using component mode primitives (IOBUF usage with IDDRE1, ISERDESE3, ODDRE1, OSERDESE3, or FDCE/FDPE/FDRE/FDSE with IOB=TRUE)

Design Advisories Alerted on April 17th, 2017

(Xilinx Answer 69034)Design Advisory for 7 Series, UltraScale and UltraScale+, all versions of Vivado prior to 2016.3 failed to include Flight time delays for differential I/O Standards.

Design Advisories Alerted on April 10th, 2017

(Xilinx Answer 68832)Design Advisory for UltraScale FPGA, UltraScale+ FPGA, and Zynq UltraScale+ MPSoC eFUSE Programming with Vivado 2016.4 (and earlier)

Design Advisory Alerted on December 26th, 2016

(Xilinx Answer 68169)Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs - New minimum production speed specification version (Speed File) required for all designs

Design Advisory Alerted on December 19th, 2016

 

(Xilinx Answer 67645)Design Advisory for 7 Series and UltraScale Architecture FPGA configuration fallback and POST_CRC limitation

Design Advisories Alerted on October 31, 2016

(Xilinx Answer 68006)Design Advisory for Xilinx Design Tools (Vivado, SDAccel, SDSoC) 2016.1 and 2016.2 write_bitstream - Multi-threading might cause configuration memory cells to be set incorrectly

Design Advisory Alerted on December 21st, 2015

(Xilinx Answer 65792)Design Advisory for UltraScale RSA Authentication - UltraScale devices that use RSA authentication will fail bitstream authentication when smaller configuration interface widths are used.

 

Design Advisories Alerted on July 06, 2015

(Xilinx Answer 64838)Design Advisory for UltraScale FPGA Transceivers Wizard: GTH Production Updates in Vivado 2015.2

 

Design Advisories Alerted on December 01, 2014

 

(Xilinx Answer 62870)Design Advisory for package changes for Virtex UltraScale devices and Kintex UltraScale devices

 

Design Advisories Alerted on November 10, 2014

(Xilinx Answer 62631)Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 Series and UltraScale FPGAs

Design Advisories Alerted on September 8, 2014

(Xilinx Answer 61903)Design Advisory for Virtex UltraScale ASCII Package Files Update

Linked Answer Records

Child Answer Records

AR# 61930
Date 07/20/2017
Status Active
Type Design Advisory
Devices
  • Virtex UltraScale
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