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AR# 61946

Virtex Ultrascale GTY - UG578 v1.0 - incorrect description for reference clock selection above 16.375 Gbps


UG578 v1.0 states on page 19 that for line rates above 16.375 Gbps a reference clock input local to the quad must be used.

This needs to be more restrictive.


For line rates > 16.375 Gbps:

  • QPLL0 can only be driven from GTREFCLK0
  • QPPL1 can only be driven from GTREFCLK1

This will be updated in the next version of the user guide.

The UltraScale Transceiver Wizard already follows this restriction.

AR# 61946
Date Created 09/08/2014
Last Updated 09/16/2014
Status Active
Type General Article
  • Virtex UltraScale
  • UltraScale FPGA Transceiver Wizard