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AR# 61963

FIR Compiler v7.2 System Generator block behavioral simulation mismatches the implemented netlist.

Description

The FIR Compiler v7.2 System Generator block behavioral simulation can mismatch the implemented netlist for the following configuration:
 
  • Coefficient width = 36 bits
  • Symmetric coefficient structure
  • 7 Series device

Solution

This is a Known issue with the FIR complier v7.2.

Workaround:
 
Increasing (or reducing) the specified coefficient width will resolve the mismatch.

The mismatch is due to an error in the calculated latency figure used by the System Generator simulation model.
AR# 61963
Date Created 09/09/2014
Last Updated 10/08/2014
Status Active
Type General Article
IP
  • FIR Compiler