UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62058

2014.2 Vivado HLS - Generated RTL code has "x" value comparisons which may lead to incorrect post-synthesis simulation result.

Description

When doing post-synthesis simulation using XST with HDL generated by Vivado HLS, there is a simulation mismatch.

Before RTL synthesis, output is expected. 

After synthesis, post-synthesis simulation output is all 0.

There is no such issue with Vivado Synthesis. 

What can cause this behavior?

Solution

This issue occurs on  "x" value comparisons.
 
XST synthesizes the code differently to Vivado Synthesis and ties output to 0.
 
Sample code:
 

assign a_tdata  = din0_buf1==='bx ? 'b0 : din0_buf1;

 
To work around this issue, you will need to change the code, for example:
 

assign a_tdata  = din0_buf1;


This issue is still under investigation and is expected to be fixed in a future release of Vivado HLS.
AR# 62058
Date Created 09/16/2014
Last Updated 03/05/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite
  • ISE