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AR# 62094

2014.2 Kintex/Virtex Ultrascle - False DRC warning related to DSP48 pipelining


False warnings are occasionally reported for DSP48 pipelining in cases with valid pipelining configurations:

WARNING: [Drc 23-20] Rule violation (DPOP-2) Output pipelining - DSP gen_ten_speed.ten_speed_top_1/pcpu_ten_speed_xfi_inst/TenGMacPCS_inst/TxMac/GenPortStats.PortLevelStats/StatCntrs/CntrDSP output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.


This false warning is scheduled to be corrected in the 2014.4 release. 

In the meantime the specific DRC check can be disabled with the following property:

set_property IS_ENABLED 0 [get_drc_checks {DPOP-2}]

AR# 62094
Date Created 09/18/2014
Last Updated 09/23/2014
Status Active
Type General Article
  • Kintex UltraScale
  • Vivado Design Suite - 2014.3