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AR# 62096

2014.2 SysGen - Too many clocks generated in a multi-clock domain design


I am following the guidelines in UG897 for creating a design that has multiple distinct clock domains in a single System Generator model.

However, the generated design is not behaving correctly.

I have discovered that Sysgen is generating three clock domains instead of just the two that I expected.

Is this a known issue?


This occurs under certain conditions in 2014.2 but is resolved in the 2014.3 release.

Please update to 2014.3 or later.
AR# 62096
Date Created 09/18/2014
Last Updated 10/08/2014
Status Active
Type General Article
  • Vivado Design Suite - 2014.2
  • System Generator for DSP