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AR# 62097

2014.2 SysGen - CORDIC v6.0 instance causes incorrect behavior elsewhere in model

Description

I have a working System Generator design and I wish to add an instance of the CORDIC v6.0 IP to the design in a completely independent and unrelated area (i.e. the signals to/from CORDIC do not interact with the rest of the design at all).

However, when I add the IP, the rest of the design starts to fail in unexpected ways.

For example, the output of a 'delay' or 'register' block will be held to '0' even though the input is '1.'

Why is this happening?

Solution

This is a known issue for some configurations and IPs discovered in Vivado Design Suite 2014.2.

The issue has been fixed in all known cases in the 2014.3 release.

Here is some data collected about the issue in case you run into it in the future:
 
  • The interaction seems to be with the CORDIC and delay or register blocks
  • Changing the CORDIC's input sample rate changes the behavior
  • Placing the CORDIC block (and possibly other surrounding blocks) in a subsystem seems to resolve the issue in the 2014.2 release.



AR# 62097
Date Created 09/18/2014
Last Updated 10/08/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.2
  • System Generator for DSP
IP
  • CORDIC