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AR# 62113: UltraScale Power - When not following the recommended power-down sequence an increased current is observed on VCCAUX as VCCINT is powering-off. Is this expected? Will the increased draw impact device reliability?
UltraScale Power - When not following the recommended power-down sequence an increased current is observed on VCCAUX as VCCINT is powering-off. Is this expected? Will the increased draw impact device reliability?
In the UltraScale families, the recommended power-up and power-up/down sequences are defined in the DC and AC Switching Characteristics Data sheet for the family in question.
An example recommended sequence for power-on is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO, while power-down would be the reverse: VCCO,VCCAUX_IO, VCCAUX, VCCBRAM, and VCCINT.
Xilinx does not characterize all power-on/power-off sequences but it has been observed in UltraScale that when VCCINT powers off before VCCAUX, VCCAUX can see an increase in current while VCCINT powers-down.
Is this expected?
Will this cause reliability concerns?
During power-down testing, Xilinx has
found that on some devices VCCAUX can experience a high current draw when VCCINT is powering down.
This is normal behavior for the device that will not cause any reliability concerns.
More than 3A of current draw on the VCCAUX supply has been observed as VCCINT falls in the range of 0.75V and 0.5V.
There are no concerns for reliability with this issue, but it might be important to understand with designs that monitor VCCAUX current during power-down.
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