We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62118

Why are there LUT2, LUT3, LUT4, LUT5, LUT6 primitives as buffers for some of my clocks in the clock networks report? Why is the D-input of the register the load and not the C (clock) input?


When analyzing the clock network, in some designs Vivado shows LUT primitive buffers for my clocks:

In some cases, the input of the register is shown in the clock network report:


Is this expected behavior of the clock networks report?


"report_clock_networks" traces down every clock in design. 

A clock is a signal that drives either the G-input of a latch or the clock inputs of sequential elements like registers, block RAMs and DSPs.

As soon as a signal is identified as a clock, it will show the entire tree of that signal from the source to all of the loads, including the non-sequential elements like LUTs.

An improvement is planned to add a filter in the clock networks report and only show the sequential elements.

The clock networks report shows the real situation of the design. 

If the clock is buffered by a LUT, this will be shown in the clock networks report.

AR# 62118
Date Created 09/21/2014
Last Updated 11/19/2014
Status Active
Type General Article
  • Vivado Design Suite