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AR# 62127

2014.2 Vivado Placer - Routing conflict created by poor placement of unanchored IODELAY cell

Description

Designs will occasionally contain an unanchored IODELAY cell, an IODELAY component that is used to delay a fabric signal and so has no I/O connections to guide placement. 

Normally the placer will select an unused I/O tile to place such a configuration so as not to interfere with the routing in a used I/O tile. 

A case has been seen where the placer failed to use an otherwise unused I/O tile and so the following routing conflict occurred:

CRITICAL WARNING: [Route 35-54] Net: down_to[0][rdata]_inferred_i_24__40/O is not completely routed. Resolution: Run report_route_status for more information.

 Unroutable connection Types:

 ----------------------------

Checking all reachable nodes within 5 hops of driver and load

Unroute Type 1 : Site pin does not reach interconnect fabric

Type 1 : HPIOB.I->SLICEL.H4

-----Num Open nets: 1

-----Representative Net: Net[18536] down_to[0][rdata]_inferred_i_24__40/O

-----IOB_X0Y318.I -> SLICE_X56Y366.H4

-----Driver Term: down_to[0][rdata]_inferred_i_24__40/IBUFCTRL_INST/O Load Term [106298]: gen_cpu_support.cpu_support_0/octeon_cpu_support_i/i_regs/share_logic.regs[1].reg_i/down_to[0][rdata]_inferred_i_6__54/I1 Driver Pin does not reach Interconnect fabric within 5 hops.

-------------------------------------------- This is from the Steps to Reproduce Problem

 -------------------------------------------- Please see attached DCP.

Solution

This problem can be avoided by choosing an unused I/O tile and constraining the unanchored cell to the BITSLICE_RX_TX_X?Y? site in that tile:

set_property LOC {BITSLICE_RX_TX_X0Y312} [get_cells IODELAY_CELL_NAME] 
AR# 62127
Date Created 09/22/2014
Last Updated 10/08/2014
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1