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AR# 62157

Design Advisory for UltraScale/UltraScale+ QDRII+ IP - Pinout DRC violations not caught in I/O Planner

Description

Version Found: v5.0 Rev1

Version Resolved: See (Xilinx Answer 69038)

The default pinout provided by MIG UltraScale does not contain any pinout violations.

However, if pins are moved in the I/O Planner it is possible DRC violations will not be caught.

If MIG UltraScale QDRII+ designs contain pinout violations, hardware failures might occur.

Below is a list of all of the MIG UltraScale QDRII+ DRC rules the I/O Planner does not detect:

Read Data (Q) Allocation:

  • All byte lanes that are used for read data of a single component must be adjacent, no skip byte lanes are allowed.
  • All of the Read Data pins of a single component should not span more than 3 consecutive byte lanes.
  • If a byte lane is used for read data, Bit[0] and Bit[6] must be used.
    Read clock (CQ or CQ#) gets the first priority and data (Q) is the next, because CQCQ# must be allocated to either Bit[0] or Bit[6].

Read Clock (CQ/CQ#) Allocation:

  • Read Clock pair must be allocated in one of the byte lanes that are used for the read data of the corresponding memory component.
  • CQ/CQ# must be allocated only in the center byte lanes (byte lanes 1 and 2) because other byte lanes cannot forward the clock out for read data capture.

Memory Clock (K/K#) Allocation:

  • Memory clock should come from one of the center byte lanes (byte lanes 1 & 2).

Address/Control (A/C) Pins Allocation:

  • All A/C byte lanes should be contiguous and no skipping of byte lanes is allowed.
  • There should not be any empty byte lane or read byte lane between A/C and write data byte lanes.
    This rule applies when A/C and write data share the same bank or are allocated in adjacent banks.

Solution

These DRC violations have been fixed in Vivado 2014.3 using MIG UltraScale v6.0 but it is possible that these violations exist for older designs which will cause DRC violations when updating IP.

These are valid violations and require all customers to re-customize and fix pinout violations.

Revision History:

10/06/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
61930 Design Advisory Master Answer Record for Virtex UltraScale FPGA N/A N/A
69038 UltraScale/UltraScale+ QDRII+ - Release Notes and Known Issues N/A N/A
AR# 62157
Date 01/11/2018
Status Active
Type Design Advisory
Devices
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
Tools
  • Vivado Design Suite
  • Vivado Design Suite - 2014.2
IP
  • QDRII+ SRAM
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