For address/Control banks, when Address Multiplex is enabled, address pins are occupying CC pins, hence there is no option for system clock pins.
However, when address multiplex is disabled, address/control pins are not allocated to CC pins and hence there are CC pins available for the system clock.
The core can be generated by disabling the Address Multiplex option or by selecting the system clock as No Buffer and driving it internally.
This is a software pin allocation issue, if you want to generate the core for the given configuration open a webcase for assistance.
Note: The "Version Found" column lists the version the problem was first discovered. The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions