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AR# 62159

MIG 7 Series - Cannot generate the IP for certain configurations of RLDRAM-II

Description

Version Found: MIG 7 Series v2.0 Rev3
Version Resolved: See (Xilinx Answer 54025)

When I try to generate the core for the below settings I do not see room for system clock allocation:
 
MemoryDevice :     RLDRAM_II,     MT44k32m18xx-125e
TimePeriod:    2222
input clock period 2222
DataWidth:     18
SystemClock    Single-Ended
ReferenceClock Single-Ended
Address Mux  Multiplexed

Solution

As per the MIG design guidelines, the System clock should come from CC pins but CC pins are present in T1 and T2 byte lanes of each bank.

When DQ pins are allocated in T1 and T2 byte lanes, the system clock cannot be allocated in the DQ bank as CC pins will be used.

For address/Control banks, when Address Multiplex is enabled, address pins are occupying CC pins, hence there is no option for system clock pins.

However, when address multiplex is disabled, address/control pins are not allocated to CC pins and hence there are CC pins available for the system clock.

 

The core can be generated by disabling the Address Multiplex option or by selecting the system clock as No Buffer and driving it internally. 

This is a software pin allocation issue, if you want to generate the core for the given configuration open a
webcase for assistance.

 


Note: The "Version Found" column lists the version the problem was first discovered. The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 62159
Date Created 09/23/2014
Last Updated 10/08/2014
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series