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AR# 62165

Vivado - Synthesis - ERROR: [Synth-1716] cannot access 'i' from inside pure function 'foo'.

Description

I am receiving the following error in Vivado Design Suite:

ERROR: [Synth-1716] cannot access 'i' from inside pure function 'foo'.


The error is being received when synthesizing the below code.

How can I avoid this?

entity Test is
    port (
        Clk : in std_logic;
        Rst : in std_logic;

        I : in std_logic_vector(10 downto 0)
        );
end entity;

architecture RTL of Test is
    function foo(X : in integer) return std_logic_vector is
    begin
        return conv_std_logic_vector(X,I'length);
    end function;
begin
end architecture;

Solution

According to the VHDL LRM, Functions are of type "pure" unless otherwise specified.

Pure functions can only take in signals or constants, not variables.

This is why the error is being displayed.

To make the example code work, you will need to make the function "impure".

To make it impure, change the function definition from :
 

function foo(X : in integer) return std_logic_vector is 

to:
 

impure function foo(X : in integer) return std_logic_vector is 

AR# 62165
Date Created 09/24/2014
Last Updated 10/08/2014
Status Active
Type Known Issues
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite