I am receiving the following error in Vivado Design Suite:
ERROR: [Synth-1716] cannot access 'i' from inside pure function 'foo'.
The error is being received when synthesizing the below code.
How can I avoid this?
entity Test is
Clk : in std_logic;
Rst : in std_logic;
I : in std_logic_vector(10 downto 0)
architecture RTL of Test is
function foo(X : in integer) return std_logic_vector is