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AR# 62192

Tandem PROM/PCIe - 2014.2/3 - How to add a debug_core to a Tandem PROM/PCIe design


How can I add a debug_core to a Tandem PROM/PCIe design?


Create a Tcl file and add the following commands. 

Run this during pre_place.

# Add all of the bufgs to the bufg PBLOCK. (This is done by build_stage1.tcl, but the debug hub and associated bufg was inserted after build_stage1.tcl)
add_cells_to_pblock [get_pblocks bufg_pblock_boot] [get_cells -hierarchical -filter { PRIMITIVE_TYPE == CLK.gclk.BUFG || PRIMITIVE_TYPE == CLK.gclk.BUFGCTRL } ]

# Resize the stage1 config pblock to include all of the BSCANprimitives
resize_pblock [get_pblocks startup_pblock_boot] -add [get_sites -filter { NAME =~  "*BSCAN*" }]

# Add the BSCAN to the config stage1 pblock.
add_cells_to_pblock [get_pblocks startup_pblock_boot] [get_cells -hierarchical -filter { PRIMITIVE_TYPE == OTHERS.others.BSCANE2 } ]

2014.4 will move build_stage1.tcl to a place.pre tcl script (rather than opt.post) and add handling for BSCAN primitives automatically.

It is important to note that only the BSCAN primitive will be part of the Tandem stage1 bitfile. 

The remainder of the debug core will be in stage2.

As result the debug core will only work when both stage1 and stage2 are loaded into the FPGA as expected.

AR# 62192
Date Created 09/25/2014
Last Updated 12/08/2014
Status Active
Type General Article
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.3