I have created an IPI system targeting a Xilinx development board.
The design includes MicroBlaze, MIG 7 Series and other IPs.
I am using connection automation and generated target outputs for the OOC of the Block design.
The Block Design level DCP is generated but in the log file I see the below critical warning:
CRITICAL WARNING: [Constraints 18-1056] Clock 'sys_clk' completely overrides clock 'sys_diff_clock_clk_p'
Is this a valid warning?
How can I resolve it?
This is a valid critical warning.
The reason for the warning is that the create_clock constraint is being applied on the same port by two different XDCs.
The create_clock constraint for the sys_clk port in IP level XDC overwrites the constraint at the Block Diagram level.
As a workaround, open the MIG generated XDC and remove the -name in the create_clock constraint.
For example, change the following:
create_clock -name sys_clk -period 5 [get_ports sys_clk_p]
create_clock -period 5 [get_ports sys_clk_p]
Then reset the OOC output products for the Block Design and re-launch the OOC run for Block Design.
09/29/2014 - Initial Release