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AR# 62204

MIG 7 series - IPI Design Create Clock Constraint Critical Warning - Constraints 18-1056 Clock 'sys_clk' completely overrides clock 'sys_diff_clock_clk_p'


Version Found: MIG 7 Series v2.0 Rev3
Version Resolved: See (Xilinx Answer 54025)
I have created an IPI system targeting a Xilinx development board.

The design includes MicroBlaze, MIG 7 Series and other IPs.
I am using connection automation and generated target outputs for the OOC of the Block design.
The Block Design level DCP is generated but in the log file I see the below critical warning:

CRITICAL WARNING: [Constraints 18-1056] Clock 'sys_clk' completely overrides clock 'sys_diff_clock_clk_p'

Is this a valid warning?

How can I resolve it?


This is a valid critical warning.

The reason for the warning is that the create_clock constraint is being applied on the same port by two different XDCs. 

The create_clock constraint for the sys_clk port in IP level XDC overwrites the constraint at the Block Diagram level. 

As a workaround, open the MIG generated XDC and remove the -name in the create_clock constraint.

For example, change the following:

create_clock -name sys_clk -period 5 [get_ports sys_clk_p]


create_clock  -period 5 [get_ports sys_clk_p]

Then reset the OOC output products for the Block Design and re-launch the OOC run for Block Design.
Revision History
09/29/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 62204
Date Created 09/26/2014
Last Updated 11/24/2014
Status Active
Type Known Issues
  • Kintex-7
  • Virtex-7
  • Artix-7
  • Vivado Design Suite - 2014.2
  • MIG 7 Series