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AR# 62209

Vivado Synthesis - Error:[Synth 8-355] interface mismatch for formal interface port 'i': i2 vs. interface

Description

Vivado Synthesis gives the following error on "interface.modport_name reference_name" System Verilog coding structure.

Error:[Synth 8-355] interface mismatch for formal interface port 'i': i2 vs. interface


The below Coding example causes this error:

interface i2; 
wire a, b, c, d; 
modport master (input a, b, output c, d); 
modport slave (output a, b, input c, d); 
endinterface 

module m (interface.master i); 
assign i.c = 1'b0;
assign i.d = 1'b1; 
endmodule 

module top (output x,y); 
i2 i(); 
assign x = i.a;
assign y = i.b;
m u1(.i(i)); 
endmodule 

What is the problem in this code?

Solution

The "interface.modport_name reference_name" structure is a hierarchical reference to any interface with a given modport name.

This is compatible with the IEEE 1800-2012 System Verilog LRM but is not supported in Vivado Synthesis.

To resolve this error, the specific interface name has to be used instead of the "interface" keyword in the hierarchical reference to the modport.
 
The following is the modified code that passes Synthesis in Vivado:
 
interface i2; 
wire a, b, c, d; 
modport master (input a, b, output c, d); 
modport slave (output a, b, input c, d); 
endinterface 

module m (i2.master i); 
assign i.c = 1'b0;
assign i.d = 1'b1; 
endmodule 

module top (output x,y); 
i2 i(); 
assign x = i.a;
assign y = i.b;
m u1(.i(i)); 
endmodule 

AR# 62209
Date Created 09/26/2014
Last Updated 01/21/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite