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AR# 62265

AXI Memory Mapped to PCI Express v2.5 - Incorrect default clock placement for KC705 Board

Description

Version Found: v2.5
Version Resolved and other known issues: (Xilinx Answer 54646)

When using the AXI Memory Mapped to PCI Express v2.5 core example design for a KC705 board, it will not link up due to incorrect clock placement.

Solution

To fix the issue, locate the top level design constraint file (usually named xilinx_axi_pcie_7x_ep_<link_config>_<blk_locn>.xdc) 

Replace the following constraint:

set_property LOC IBUFDS_GTE2_X0Y3 [get_cells refclk_ibuf]

with:

set_property LOC IBUFDS_GTE2_X0Y1 [get_cells refclk_ibuf]

Revision History:
10/06/2014 - Initial Release

AR# 62265
Date Created 09/29/2014
Last Updated 10/08/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.3
IP
  • AXI PCI Express (PCIe)
Boards & Kits
  • Kintex-7 FPGA KC705 Evaluation Kit