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AR# 62276

Vivado - Why do I get DRC ERRORs during Bitstream generation when no ERRORs were issued previously in the flow?


In my design, I am receiving no Errors until the project flows gets to Bit Stream generation.

Then Vivado reports some Errors that were not reported before which stop the process.

Why does this happen?


During the design flow, Vivado will report all of the same problems that are flagged as ERRORs in the bitstream generation stage.  

However, during the synthesis and implementation stages of the design flow, some of the same DRC issues are considered non-critical so they are reported as simple Warnings or Critical Warnings.  

This allows the flow to continue so that you can verify other portions of the design that are not affected by the flagged DRC issue.

At the final stage, there are some problems that need to be solved before generating the Bit file.

In these cases, the initial DRC Warnings/Critical Warnings will be turned into Errors.

AR# 62276
Date 12/12/2014
Status Active
Type General Article
  • SoC
  • FPGA Device Families
  • Vivado Design Suite
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