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AR# 62281

System Generator - Dual Port RAM block producing error when initial vector is set incorrectly

Description

My Multiple Clock Domain design in System Generator is failing due to an error in the Dual Port RAM block initialization.

In 2014.2, the following error is reported which does not provide any information on what is wrong:

--------------------------------- Version Log ----------------------------------
Version                                 Path
System Generator 2014.2                 C:/Xilinx/Vivado/2014.2
Matlab 8.3.0.532 (R2014a)               C:\MATLAB\R2014a
Vivado 2014.2                           C:/Xilinx/Vivado/2014.2
--------------------------------------------------------------------------------
Summary of Errors:
Error 0001: Internal Error
     Block: 'DPRAM_async_ports_example1/Dual Port RAM'
--------------------------------------------------------------------------------

Error 0001:

Reported by:
  'DPRAM_async_ports_example1/Dual Port RAM'

Details:
An internal error occurred in the Xilinx Blockset Library.

Please report this error to Xilinx (http://support.xilinx.com),
in as much detail as possible. You may also find immediate help
in the Answers Database and other online resources at http://support.xilinx.com.


Error occurred during "Simulation Update State".

In 2014.3, the following error is reported which gives more information but still does not state exactly what is wrong and how it can be resolved:

--------------------------------- Version Log ----------------------------------
Version                                 Path
System Generator 2014.3                 /proj/xbuilds/2014.3_0930_1/installs/lin64/Vivado/2014.3
Matlab 8.3.0.532 (R2014a)               /tools/gensys/matlab/R2014a
Vivado 2014.3                           /proj/xbuilds/2014.3_0930_1/installs/lin64/Vivado/2014.3
--------------------------------------------------------------------------------
Summary of Errors:
Error 0001: ERROR:Attempt to access address location 1, exceeds the i...
     Block: 'DPRAM_async_ports_fifo/Dual Port RAM'
--------------------------------------------------------------------------------

Error 0001:

Reported by:
  'DPRAM_async_ports_fifo/Dual Port RAM'

Details:
ERROR:Attempt to access address location 1, exceeds the index of
initial data vector (of size 1) specified for port A of dual port
RAM.

Error occurred during "Simulation Update State".

--------------------------------------------------------------------------------

What is causing these errors and how can I fix them?

Solution

These errors occur when the Dual Port RAM is configured to a depth greater than 1 but a vector value is not entered in the "Initial value vector" text field.

incorrect_value62281.JPG

If the desired outcome is to initialize the block RAM to all zeros, then the following should be applied:

correct_value62281.JPG





 

AR# 62281
Date Created 09/30/2014
Last Updated 03/05/2015
Status Active
Type General Article
Tools
  • System Generator for DSP
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.3
IP
  • Dual Port Block Memory