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AR# 62291

2014.3 Vivado IP Flows - CRITICAL WARNING: [filemgmt 20-1741] File 'builtin_prim_v6.vhd' is used by one or more modules, but with different contents, and may lead to unpredictable results:

Description

I have a Vivado project containing an IP Integrator (IPI) block diagram (BD).  

The project compiles and implements with no issues in Vivado 2014.2. 

However, when I open the design in Vivado 2014.3, synthesis fails even though I have upgraded the BD.

I receive errors and critical warnings similar to the following:
 

ERROR : [Synth 8-2396] near character '0' ; 3 visible types match here ["/proj/proj.2.srcs/sources_1/ipshared/xilinx.com/blk_mem_gen_v8_2/19f733e6/hdl/blk_mem_gen_generic_cstr.vhd":1924] [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details.


CRITICAL WARNING: [filemgmt 20-1741] File 'builtin_prim_v6.vhd' is used by one or more modules, but with different contents, and may lead to unpredictable results: * system_top_v_tpg_1_0 (/proj//proj.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/8b540c64/hdl/builtin/builtin_prim_v6.vhd) * system_top_axi_perf_mon_1_0 (/proj/proj.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/d0c48dec/hdl/builtin/builtin_prim_v6.vhd) Please reset and regenerate these modules to resolve the differences, or synthesize them independently.

Solution

The error occurs because an RTL file is out of sync and the type of a signal is not properly declared.

These errors can be caused if the HDL files generated for the IP of a Block Design become out of sync.
 
Many IP used in Vivado contain subcores of other IP (for example FIFO uses a BRAM subcore). 

If an IP undergoes a version or revision change, any IP using a subcore of this IP also need to have a revision change in order to keep in sync with the child IP core.

In Vivado 2014.3, there were some IP that correctly made the revision change but a small number that did not. 

This error or critical warning will occur if a BD contains a combination of IP that use the same subcore where at least one of the IP did not update the revision and at least one of the IP did update the revision.

To solve this problem, reset the BD output products after upgrading the BD.
 
Note: In an RTL flow, users will not typically see this issue because out of context (OOC) synthesis is run by default on each IP core. 

This keeps the files of each IP core independent of other IP cores.

In Vivado 2014.3, BD synthesis does not have OOC synthesis available.

AR# 62291
Date Created 09/30/2014
Last Updated 10/08/2014
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2014.3