I have a Vivado project containing an IP Integrator (IPI) block diagram (BD).
The project compiles and implements with no issues in Vivado 2014.2.
However, when I open the design in Vivado 2014.3, synthesis fails even though I have upgraded the BD.
I receive errors and critical warnings similar to the following:
[Synth 8-2396] near character '0' ; 3 visible types match here ["/proj/proj.2.srcs/sources_1/ipshared/xilinx.com/blk_mem_gen_v8_2/19f733e6/hdl/blk_mem_gen_generic_cstr.vhd":1924]
[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details.
CRITICAL WARNING: [filemgmt 20-1741] File
'builtin_prim_v6.vhd' is used by one or more modules, but with different
contents, and may lead to unpredictable results:
Please reset and regenerate these modules to resolve
the differences, or synthesize them independently.