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AR# 62320

MIG 7 Series DDR2 - DQS overshoot on 200MHz design when CL=3

Description

 

Version Found: v2.1
Version Resolved: See (Xilinx Answer 54025)
The MIG 7 Series DDR2 design may experience DQS overshoot due to Taond violation when running at 200MHz and targeting a CAS Latency of 3 (CL=3).

 

 

Solution


When 200MHz DDR2 with CL=3 is targeted, MIG PHY drives ODT later than the time required for the Taond specification so that DQS may overshoot on the first cycle of write operation.

This does not affect read or write operation or calibration, however may violate DQS DC specification.

To resolve the violation, set CAS latency = 4 in the core_name_mig.v file.

   ---CL                    : integer := 3;
       CL                    : integer := 4;

 

Revision History:

10/07/2014 - Initial Release

 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 62320
Date Created 10/01/2014
Last Updated 10/15/2014
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1
  • More
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2013.3
  • Less
IP
  • MIG 7 Series