In UltraScale FPGA, how can I interface a STARTUPE3 primitive to axi_emc_ip or axi_quad_spi_ip so that I can access parallel NOR/BPI flash or QSPI flash after configuration?
The AXI EMC and AXI QUAD SPI IP cores do not currently support the automatic instantiation of the STARTUPE3 primitive.
The STARTUPE3 primitive must be manually instantiated in the top module to access flash in post-configuration mode.
The user must instantiate and connect the STARTUPE3 primitive in their top level design file to enable post-configuration access to the flash.
The files attached provide a reference example design and more information on how to use the STARTUPE3.
The designs attached were created and tested with Vivado Design Suite 2015.2. To build the design please read the respective "README.TXT" file for more information.
This issue exists in Vivado software starting from 2014.x up to 2015.2. Vivado Design Suite 2015.3 is targeted to have the option to automatically add the STARTUPE3 primitive when needed from the AXI_QSPI or AXI_EMC IP.