UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62395

2013.2 Partial Reconfiguration - Empty module inside of RM fails to be optimized away

Description

In my design, there is a module inside of the RM with logic that should be optimized away.
 
However, the actual hierarchical cell of the module cannot be removed because the clock net that connects to it has a DONT_TOUCH attribute on it.
 
In this design, the DONT_TOUCH attribute has to be added to nets inside of the RM to prevent certain optimizations.
 
I am receiving the following error messages during opt_design:
 

ERROR: [Opt 31-120] Instance 'adder_cw_i/persistentdff_inst (xlpersistentdff)' has become an empty hierarchy during sweep, however it has constraints that do not permit its removal.
Resolution: Please check for dont_touch property or timing-constraint set on the empty hierarchy. If found, remove the relevant dont_touch property or timing constraint and re-run opt_design.
ERROR: [Opt 31-120] Instance 'adder_cw_i (adder_cw)' has become an empty hierarchy during sweep, however it has constraints that do not permit its removal.
Resolution: Please check for dont_touch property or timing-constraint set on the empty hierarchy. If found, remove the relevant dont_touch property or timing constraint and re-run opt_design.
INFO: [Opt 31-11] Eliminated 3 unconnected cells.

Solution

This issue is fixed in the 2013.3 release of Vivado Design Suite.
AR# 62395
Date Created 10/08/2014
Last Updated 02/24/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2013.2