I am simulating a Vivado HLS model, and in the design there is an Assert block on a Floating-point precision input signal ("provide output port" enabled on the Assert block).
The simulation output of the Vivado HLS model is invalid.
However, If I remove the Assert block, the simulation results of the Vivado HLS model correspond to the original simulation results from the Vivado HLS program.
This is the Known issue in Vivado Sysgen 2014.3.
This has been fixed in the 2014.4 release of Vivado.