I am using Vivado Design Suite 2014.3.
If Vivado Synthesis encounters multiple create_clock constraints on the same clock port, a crash may occur when using a Windows OS with the following output:
This issue has been resolved in the 2014.4 release, and a tactical patch has been created to address this issue in 2014.3.
Expectations with a patch:
Expectations without a patch:
To work around this issue without installing a patch:
1) If the multiple overwriting create_clock constraints are due to a user constraint file:
a) Delete or change the name of one of the multiple clock constraints so that they are no longer identical. For example:
create_clock -name CLK_25_TCXO [get_ports <clock_port>]
create_clock -name CLK_25_TCXO_new [get_ports <clock_port]
b) Set the USED_IN_SYNTHESIS property of the user constraint file to FALSE:
set_property USED_IN_SYNTHESIS FALSE [get_files <user_constraint_file>.xdc]
2) If the multiple overwriting create_clock constraints are due to overlapping IP:
Set the IP to run in Out-Of-Context mode and to be read in after Synthesis:
set_property generate_synth_checkpoint TRUE [get_ip <ip_name>]
set_property USED_IN_SYNTHESIS FALSE [get_ip <ip_name>]
Optionally you can also right click the IP and select Out-Of-Context settings to enable OOC mode.
Implementing any of the above workarounds will successfully bypass the crash.
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