This Design Advisory covers the MIG UltraScale cores.
When DCI Cascading is not used, all I/O banks containing memory interface pins require the VRP pin to be connected.
This includes output only banks such as a bank used for only Address/Control pins.
DCI cascading cannot be supported for interfaces running above 2133Mbps.
This affects all types of memory interfaces generated by MIG UltraScale.
Designs not using DCI Cascading:
The requirement to connect a VRP pin in all I/O banks, including output only banks, exists because all I/Os (except "reset_n") use a DCI I/O Standard and therefore require VRP.
The addition of the DCI standard for outputs (for example, SSTL*_DCI) was introduced in 2014.4 in order to use controlled output impedance.
Outputs previously used the uncalibrated output impedance option instead of the controlled DCI version that calibrates to an external reference resistor on the VRP pin.
The controlled output impedance adds a calibration routine to compensate for temperature, process, or voltage variations.
All rules for DCI in the UltraScale Architecture-Based FPGAs SelectIO Resources User Guide (UG571) must be followed.
The only pin that does not follow this requirement is reset_n because it does not use a DCI I/O Standard.
If reset_n is placed in a non-memory interface bank, that bank does not need VRP.
For additional information, please refer to the UltraScale Architecture FPGAs Memory IP Product Guide (PG150).
Design using DCI Cascading:
DCI cascading can be supported for interfaces running at and below 2133Mbps.
(PG150) and the Memory Interface wizards will be updated with the release of Vivado 2016.1 to include the DCI Cascading support guidelines.
All rules for DCI Cascading in the UltraScale Architecture-Based FPGAs SelectIO Resources User Guide (UG571) must be followed.
10/30/15 - Updated to include 2133Mbps and below support for DCI Cascading
10/20/14 - Initial Release