UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62498

2014.3 - Ultrascale Simulation issues with IP Cores containing the GTH/GTY/PCIE primitives

Description

If you have an Ultrascale implementation of the following IP Cores, you may have some problems with simulation.


  •         AXI_10G_ETHERNET
  •         GTWIZARD_ULTRASCALE
  •         PCIE3_ULTRASCALE
  •         TEN_GIG_ETH_PCS_PMA
  •         CMAC
  •         INTERLAKEN

Solution

Update the libraries with the attached patch.

The libraries are located under the install path:

<install_path>/Vivado/2014.3/data

Attachments

Associated Attachments

Name File Size File Type
2014.3.secureip.tar.gz 2 MB GZ

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58884 Xilinx Simulation Solution Center - Design Assistant - IP Simulation N/A N/A
AR# 62498
Date Created 10/15/2014
Last Updated 04/02/2015
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite