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AR# 62506

2014.3/2014.4 Virtex UltraScale - incorrect BRAM FMAX_ECC in pulse width check

Description

In my design, the configuration of the RAMB is block RAM and FIFO in ECC configuration with PIPELINE and Block RAM in Write First or No Change mode.

However, the value used for pulse width check is 1.887ns (530MHz) instead of 1.515ns (660MHz).

As per the datasheet, (DS893)

http://www.xilinx.com/support/documentation/data_sheets/ds893-virtex-ultrascale-data-sheet.pdf

Pg27, "Table 27: Block RAM and FIFO Switching Characteristics"

FMAX_ECC for speed grade -3 in this type of RAMB configuration is 660MHz.

Solution

This is a known issue. 

The FMAX_ECC value in this configuration should be 660MHz as documented in datasheet.

The issue will be fixed in the 2015.1 release.

AR# 62506
Date Created 10/16/2014
Last Updated 02/13/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite