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AR# 62513

2014.3 - Simulation : ERROR: [VRFC 10-280] actual for formal port "XXX" is neither a static name nor a globally static expression

Description

I am receiving the following error In Vivado Simulator 2014.3:
 

ERROR: [VRFC 10-280] actual for formal port "XXX" is neither a static name nor a globally static expression


I did not receive this error in Vivado Simulator 2014.2 with the same design.

Why does this error occur?

Solution

This error has been added to the 2014.3 release to warn that this coding style is not supported in the current version of Vivado (VHDL-93). 

However, some coding constructs from VHDL 2008 might work (there are cases where these designs simulate in 2014.2 without any problems)


Support for VHDL 2008 is planned for a future release of Vivado Simulator.

AR# 62513
Date Created 10/16/2014
Last Updated 11/26/2014
Status Active
Type General Article
Devices
  • SoC
  • FPGA Device Families
Tools
  • Vivado Design Suite - 2014.3