We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62515

AXI Bridge for PCI Express Gen3 v1.0 - VC709 example design with default PCIe Block location fails during implementation


Version Found: 1.0

Version Resolved and other known issues: (Xilinx Answer 61898)

I am implementing the AXI Bridge for PCI Express Gen3 v1.0 core example design for a VC709 board with the default PCIe Block location.

The implementation is failing with critical warnings and errors.


This is a known issue which is due to be fixed in the next release of the core.

To work around this issue, make the following changes in the default GUI:

Change settings from:


Change settings to:




Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


Revision History:
10/26/2014 - Initial Release

AR# 62515
Date 06/25/2018
Status Active
Type Known Issues
  • AXI PCIe Gen3
Page Bookmarked