Some popular applications such as oversamplers require that the Clock Data Recovery (CDR) be locked to "local reference clock".
This means that the Phase Interpolator (PI) is frozen and should not be driven by the CDR.
Another request is that the equalization frequency response be as "flat" or transparent as possible.
It is not possible to bypass the Continuous Time Linear Equalizer (CTLE), however the following solution provides a preferred CTLE and AGC configuration.
For GTY transceivers, you can apply the setup below to have the CDR always locked to the local oscillator:
1) CDR configuration
RXCDRHOLD = 1b1
RXCDROVRDEN = 1b0
2) LPM, AGC, CTLE configuration
RXLPMGCHOLD = does not matter
RXLPMGCOVRDEN = 1
RXLPM_GC_CFG = 31
RXLPMLFHOLD = does not matter
RXLPMLFKLOVRDEN = 1
RXDFELPM_KL_CFG0 = 0
RXLPMHFHOLD = does not matter
RXLPMHFOVRDEN = 1