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AR# 62530

7-Series FPGAs Transceivers Wizard - PCIe GT Wrapper support in 2014.3 and later

Description

Starting in Vivado 2014.3, PCIe GT Wrapper support has been removed from the 7 Series FPGAs Transceivers Wizard.

There will be no option to select a PCIe template in the 7 Series FPGAs Transceivers Wizard v3.4 or later.

Solution

If you need a GT wrapper for your PCIe core, generate the 7 Series Integrated Block for PCI Express v3.1 core (found in IP catalog) for the required link width and speed.

The necessary GT wrapper files can be found in the following location:

<>\<project_name>\<project_name>.srcs\sources_1\ip\pcie_7x_0\source

The GT wrapper file hierarchy to integrate into your custom PCIe core is as follows:

 pipe_wrapper.v
      pipe_reset.v or gtp_pipe_reset.v
      qpll_reset.v
          [* GTXE2_CHANNEL for every lane.]
              pipe_user.v
              pipe_rate.v or gtp_pipe_rate.v
              pipe_sync.v
              pipe_drp.v or gtp_pipe_drp.v
              pipe_eq.v
                  rxeq_scan.v
              gt_common.v
                  GTXE2_CHANNEL or GTHE2_CHANNEL or GTPE2_CHANNEL
                  GTXE2_COMMON  or GTHE2_COMMON or GTPE2_CHANNEL
         [ * GTXE2_COMMON for every quad.]
              qpll_drp.v
              qpll_wrapper.v
             gt_wrapper.v             
                 cpllpd_ovrd.v

There are number of parameters in the *pipe_wrapper.v file, the values of which are transferred from higher level modules.

To find out the correct values of these parameters for the given core configuration, please follow the steps below.

  1. Generate the 7 Series Integrated Block for PCI Express core for the required configuration.
  2. Open the example design.
  3. Close the existing project.
  4. Create a new project for the same device.
  5. Import the following directories into the project in '4'.

 

  • <>\pcie_7x_0_example\pcie_7x_0_example.srcs\sources_1\imports\pcie_7x_0\example_design\support
  • <>\project_1\project_1.srcs\sources_1\ip\pcie_7x_0\synth
  • <>\project_1\project_1.srcs\sources_1\ip\pcie_7x_0\source

The project hierarchy should look like the below example:

hierarchy.png

                 6. Run Synthesis.

                 7. Copy the log file as shown below:

           

synthesis_log.png

              8.  In the log file, search for the parameter listing for *pipe_wrapper.v:

              INFO: [Synth 8-638] synthesizing module 'pcie_7x_0_pipe_wrapper' [C:/TestFolder/gt_wizard/project_2/project_2.srcs/sources_1/imports/source/pcie_7x_0_pipe_wrapper.v:156]
                Parameter PCIE_SIM_MODE bound to: FALSE - type: string
                Parameter PCIE_SIM_SPEEDUP bound to: FALSE - type: string
                Parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL bound to: 1 - type: string
                Parameter PCIE_GT_DEVICE bound to: GTX - type: string
                Parameter PCIE_USE_MODE bound to: 3.0 - type: string
                Parameter PCIE_PLL_SEL bound to: CPLL - type: string
                Parameter PCIE_AUX_CDR_GEN3_EN bound to: TRUE - type: string
                Parameter PCIE_LPM_DFE bound to: LPM - type: string
                Parameter PCIE_LPM_DFE_GEN3 bound to: DFE - type: string
                Parameter PCIE_EXT_CLK bound to: TRUE - type: string
                Parameter PCIE_EXT_GT_COMMON bound to: FALSE - type: string
                Parameter EXT_CH_GT_DRP bound to: FALSE - type: string
                Parameter TX_MARGIN_FULL_0 bound to: 7'b1001111
                Parameter TX_MARGIN_FULL_1 bound to: 7'b1001110
                Parameter TX_MARGIN_FULL_2 bound to: 7'b1001101
                Parameter TX_MARGIN_FULL_3 bound to: 7'b1001100
                Parameter TX_MARGIN_FULL_4 bound to: 7'b1000011
                Parameter TX_MARGIN_LOW_0 bound to: 7'b1000101
                Parameter TX_MARGIN_LOW_1 bound to: 7'b1000110
                Parameter TX_MARGIN_LOW_2 bound to: 7'b1000011
                Parameter TX_MARGIN_LOW_3 bound to: 7'b1000010
                Parameter TX_MARGIN_LOW_4 bound to: 7'b1000000
                Parameter PCIE_POWER_SAVING bound to: TRUE - type: string
                Parameter PCIE_ASYNC_EN bound to: FALSE - type: string
                Parameter PCIE_TXBUF_EN bound to: FALSE - type: string
                Parameter PCIE_RXBUF_EN bound to: TRUE - type: string
                Parameter PCIE_TXSYNC_MODE bound to: 0 - type: integer
                Parameter PCIE_RXSYNC_MODE bound to: 0 - type: integer
                Parameter PCIE_CHAN_BOND bound to: 0 - type: integer
                Parameter PCIE_CHAN_BOND_EN bound to: TRUE - type: string
                Parameter PCIE_LANE bound to: 2 - type: integer
                Parameter PCIE_LINK_SPEED bound to: 3 - type: integer
                Parameter PCIE_REFCLK_FREQ bound to: 0 - type: integer
                Parameter PCIE_USERCLK1_FREQ bound to: 3 - type: integer
                Parameter PCIE_USERCLK2_FREQ bound to: 3 - type: integer
                Parameter PCIE_TX_EIDLE_ASSERT_DELAY bound to: 3'b010
                Parameter PCIE_RXEQ_MODE_GEN3 bound to: 1 - type: integer
                Parameter PCIE_OOBCLK_MODE bound to: 1 - type: integer
                Parameter PCIE_JTAG_MODE bound to: 0 - type: integer
                Parameter PCIE_DEBUG_MODE bound to: 0 - type: integer
                Parameter TXEQ_FS bound to: 6'b101000
                Parameter TXEQ_LF bound to: 6'b001111
                Parameter GC_XSDB_SLAVE_TYPE bound to: 16'b0000000001000110

9. Update the parameter values in the pipe_wrapper.v file with the values in '8'. 

For Simulation, for the listed parameters below, overwrite the values in '8' with the values shown against the parameters below:

PCIE_SIM_MODE                               TRUE
PCIE_SIM_SPEEDUP                         TRUE
PCIE_LPM_DFE                                  DFE
PCIE_TX_EIDLE_ASSERT_DELAY       3'd4

Note: Check the XDC file generated with the core for relevant constraints.

Revision History:
11/04/2014 - Initial release





 

AR# 62530
Date Created 10/17/2014
Last Updated 02/17/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.3
IP
  • 7 Series FPGAs Transceivers Wizard