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AR# 62541

Vivado Timing - Is there a way to report the max skew of each clock net in a design?

Description

Is there a way to report the max skew of each clock net in a design?

Solution

There is no command to do this directly. 

The attached Tcl script reports the max skew of each clock network in the design by querying a user-specific number of timing paths in each clock domain. 


Instructions on using this Tcl script:

1. Open the Synthesized or Implemented design.

2. In the Tcl console, run the following command:

source <path to the script>/report_max_clock_skew.tcl
report_max_clock_skew  <# of timing paths>

"# of timing paths" in the command is an integer value which is the number of timing paths to query in each clock domain for max clock skew comparison and reporting.


Example:

source ./report_max_clock_skew.tcl

report_max_clock_skew  300


Example outputs:

The max clock skew of each clock network in setup time analysis:

The max clock skew of Clock wbClk  = -0.323

The max clock skew of Clock bftClk  = -0.026

The max clock skew of each clock network in hold time analysis:

The max clock skew of Clock wbClk  = 0.173

The max clock skew of Clock bftClk  = 0.169


Note: 

  1. The script searches the max clock skew (comparing the absolute value) within the specified number of timing paths for each clock domain.
     
    Users should define the number carefully.
    If the path number is too large it will increase the CPU's processing burden and runtime.
    If the path number is too small it might not cover the maximum clock skew value.
     
  2. Because setup time and hold time are calculated in different process corners, the script calculates the max clock skew separately.


Attachments

Associated Attachments

Name File Size File Type
report_max_clock_skew.tcl 1 KB TCL
AR# 62541
Date Created 10/20/2014
Last Updated 01/08/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite