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AR# 62566

Vivado 2014.x - Sim Models - Inverted std_ulogic parameters changed to bit - Which models are changed?


In Vivado 2014.3, a number of simulation models have their 'inverted' parameters changed from std_ulogic to bit.
This can result in issues during synthesis and simulation if the types declared in the HDL do not match the library components.

What models have been changed?


See the attached text files for a list of which models and parameters were changed.

Please ensure that you map the parameter type correctly in your design.


Associated Attachments

Name File Size File Type
unisim_change_list.txt 16 KB TXT
retarget_change_list.txt 3 KB TXT

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58895 Xilinx Simulation Solution Center - Design Assistant - Simulation Libraries - UNISIM & SIMPRIM N/A N/A
AR# 62566
Date 04/09/2015
Status Active
Type General Article
  • FPGA Device Families
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
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