We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62571

MIG UltraScale DDR4/DDR3 - Why are the impedance values not continuous within the route guideline documented in (UG583)?


(UG583)  The UltraScale Architecture PCB Design Advance Specification User Guide includes tables for the DDR4/3 PCB impedance guideline and route topology.

The impedance value is not continuous for DDR4/3 signals.

Why is this the case?


The Breakout is the connection from the pad to the last BGA ball in the array.

Via is used to route the FPGA pad to the external devices and this via is very close to the pad.

Due to small pitch of the ball of package and via width, there is not enough room to route the Breakout.

For address/control signals, to achieve 36 ohms between all of the via within the BGA grid, a very thin dielectric would be required.

This would make the layer unusable for any other signals other than memory.

In order to route 50 ohm lines on the same layer it would require the trace to be so thin it would become non manufacturable.

Therefore, the Breakout is recommended as 50ohm.

Within the figures in (UG583), L3 is 50ohm, which can help to balance the capacitive effects of the receivers.

When taking into account the whole system, it keeps a more balanced impedance across the whole line.

For the CK differential signal, the reason for non-continuous impedance on a route is similar.

AR# 62571
Date Created 10/21/2014
Last Updated 01/27/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale