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AR# 62593

UltraScale RLDRAM3 - default bank selection for 72-bit designs fails to select all data byte lanes


Version Found: RLDRAM3 v6.0

Version Resolved: See (Xilinx Answer 69037)

The default bank and byte selection for a MIG UltraScale RLDRAM3 72-bit design fails to select all data byte lanes which prevents the IP core from being generated.


To work around this issue, the remaining data byte lanes must be manually assigned to a bank and byte lane before the IP core can be successfully generated.

Revision History:

10/23/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69037 UltraScale/UltraScale+ RLDRAM3 - Release Notes and Known Issues N/A N/A
AR# 62593
Date 12/19/2017
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.4.1
  • MIG UltraScale
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