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AR# 62593

MIG UltraScale RLDRAM3 - default bank selection for 72-bit designs fails to select all data byte lanes


Version Found: MIG UltraScale v6.1
Version Resolved: See (Xilinx Answer 58435)

The default bank and byte selection for a MIG UltraScale RLDRAM3 72-bit design fails to select all data byte lanes which prevents the IP core from being generated.


To work around this, the remaining data byte lanes must be manually assigned to a bank and byte lane before the IP core can be successfully generated.

Revision History:
10/23/2014 - Initial Release

Linked Answer Records

Master Answer Records

AR# 62593
Date Created 10/23/2014
Last Updated 11/24/2014
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale